2725
SRAM IMC without the usual limitations
Boolean SRAM in-memory computing (IMC) is an
important component of current research, such as
hardware-based neural networks and edge computing.
In conventional approaches, several cells are usually
evaluated simultaneously via the same bit lines to
implement the AND and OR functions. However, this
causes difficulties in maintaining the stored value
during a read operation and requires larger cell layouts
due to necessary adjustments.
Subject area
Integrated Electronic Systems Lab
Patent number
DE102026101162
Contact person
Prof. Dr.-Ing Klaus Hofmann
klaus.hofmann@ies.tudarmstadt. de
+49 6151 16-20266
Downloads
The exposé is available to download here as a PDF.
In contrast to conventional IMC, our implementation
executes Boolean instructions during a write access. To
do this, an external operand (which can also be read
from the SRAM beforehand) is applied to the bit lines and
only WLAND is activated for the AND instruction, or only
WLOR for the OR instruction. For conventional setting,
both word lines are activated. After the instruction, the
result is automatically stored in the activated SRAM cell
and therefore does not need to be written back as is
usually the case.